1. Field of the Invention
The present invention relates to functional testing techniques for complex integrated circuits, and in particular, to functional testing techniques which allow such circuits to be tested more completely in both a stand-alone manner and when mounted in a circuit assembly such as on a printed circuit board.
2. Description of the Related Art
As integrated circuits (ICs) have become more complex with higher levels of circuit integration, functional testing of such ICs has become more problematic. Not only are more and more functions integrated into such ICs, thereby requiring significantly more with respect to both the number and types of functional tests, but also with so many functions built in, along with their necessary input and output connections, the sharing of package pins for input and output connections cause such tests to become increasingly complex and time consuming. Further, with integration techniques allowing such ICs to become smaller and smaller, as more and more functions are integrated into such circuits, a practical limitation is quickly encountered with respect to the number of pins which can be reasonably accommodated on the package. As the pins and the spacing between the pins become smaller and smaller, mounting such packaged ICs into circuit assemblies, e.g. on a printed circuit board, becomes more difficult with respect to avoiding misconnected or shorted pins. Accordingly, it would be desirable to have an improved system and method for allowing thorough functional testing of complex ICs which avoid these problems.